1. Field of the Invention
The present invention relates to a semiconductor package structure and a carrier thereof and more particularly, to a flip chip package structure and a carrier thereof.
2. Description of Related Art
The flip chip (FC) bonding technology is a package technology of bonding a die to a carrier in which a plurality of bumping pads are disposed on an active surface of a die in an area array and bumps are formed on the bumping pads. Then, the die is flipped and the bumping pads on the die surface are electrically and structurally connected to the contacts on the carrier through the bumps. As a result, the die is electrically connected to the carrier through the bumps and to external electronic devices through the internal circuits of the carrier. The FC bonding technology is suitable for a chip package structure with a high pin count and has many advantages such as reduced chip package area and shortened signal transmission paths. Thus, the FC bonding technology is currently widely used in the field of advanced chip packaging.
FIG. 1 is a schematic diagram of a conventional gold-tin flip chip package structure. Referring to FIG. 1, a gold-tin flip chip package structure 100 mainly comprises a chip 110, a carrier 120, and a plurality of gold stud bumps 130 connecting the chip 110 and the carrier 120. In the gold-tin flip chip package structure 100, the height of the gold stud bump 130 is low. Therefore, the gap between the chip 110 and the carriers 120 is reduced after the gold stud bump 130 is bonded with solder 122 on the carrier 120. In addition, a size of an opening of a solder mask 124 is usually designed to be larger than that of the chip 110 so as to facilitate the filling of the underfill in a following process.
In relation to the increase in the size of the opening of the solder mask 124, the length of the circuit connecting the solder mask 124 and the gold stud bump 130 becomes longer. However, the circuit has been coated with solder. Therefore, in the reflow process, the solder consolidates and bulges due to the cohesive force on the surface of the solder. FIG. 2 illustrates a distribution of where the solder consolidates of a conventional gold-tin flip chip package structure after the reflow process. The parts of bright oval shapes are the places where the solder 122 consolidates on the circuit after the reflow process. As shown in FIG. 2, the places where the solder 122 bulges are often not easily controlled and distribute irregularly. That is, the places where the solder 122 bulges on each circuit are mostly not the same.
However, referring to FIG. 3, if the places where the solder 122 bulges are away from the gold stud bump 130, it often results in a poor bonding of gold and tin and further reduces the yield of the gold-tin flip chip package structure.